Integrated circuits connect to and communicate with each other, typically using a bus with address, data and control signals. Today's complex digital circuits contain storage devices, finite-state machines, and other such structures that control the movement of information by various clocking methods. Transferred signals must be properly synchronized or linked so that information from a transmit point is properly communicated to and received by a receive point in a circuit.
The term “signal” refers to a stream of information communicated between two points within a system. For a digital signal, this information consists of a series of “symbols,” with each symbol driven for an interval of time. In digital applications, the symbols are generally referred to as “bits” in which values are represented by “zero” and “one” symbols, although other symbol sets are possible. The values commonly used to represent the zero and one symbols are voltage levels, although other variations are possible.
In some cases, a signal will be given more than one name (using an index notation), with each index value representing the signal value present at a particular point on a wire. The two or more signal names on a wire represent the same information, with one signal value being a time-shifted version of the other. The time-shifting is the result of the propagation of voltage and current waveforms on a physical wire. Using two or more signal names for the same signal information allows for easy accounting of the resulting propagation delays.
The term “wire” refers to the physical interconnection medium which connects two or more points within a system, and which serves as the conduit for the stream of information (the signal) communicated between the points. For example, but without limitation, a wire can be a copper wire, a metal (eg., copper) trace on a printed circuit board, or a fiber optic cable. A “bus” is a wire or a set of wires. These wires are collected together because they may share the same physical topology, or because they have related timing behavior, or for some other reason. The assignment of wires into a bus is often a notational convenience. The terms “line,” “connection” and “interconnect” mean either a bus, wire or set of wires as appropriate to the context in which those terms are used.
The term “signal set” refers to one or more signals. Whenever a signal or signal set is described herein as being coupled to or attached to a device or component, it is to be understood that the device or component is coupled to a wire, set of wires or bus that carries the signal.
The mapping of a signal onto a physical wire involves tradeoffs related to system speed. The use of one physical wire per signal (single-ended signaling) uses fewer wires. The use of two physical wires per signal (differential signaling) permits shorter bit intervals. The mapping of signals onto physical wires can also involve optimization related to system resources. Two different signals can share the same wire (i.e., they are multiplexed) to minimize the number of physical wires. Typically, this must be done so that the potential timing conflicts that result are acceptable (in terms of system performance, for instance).
The interval of time during which a bit or symbol is transmitted or received at a particular point on a wire or at a device interface is the “symbol time interval,” “bit time,” “bit time interval,” “bit window,” or “bit eye.” These time interval terms for transmitting and receiving are used interchangeably. Usually, the bit interval for transmit signals must be greater than or equal to the bit interval for receive signals.
In FIG. 1, a bus 20 interconnects a memory controller 22 and memory components (MEMS) 24. Physically, the bus 20 comprises traces on a printed circuit board or wiring board, wires or cables and connectors. Each of these devices 22, 24 has a bus output driver or transmitter circuit 30 that interfaces with the bus 20 to drive data signals onto the bus to send data to other integrated circuits. Each of these devices also has a receiver. In particular, the bus output drivers 30 in the memory controller 22 and MEMS 24 are used to transmit data over the bus 20. The bus 20 transmits signals at a rate that is a function of many factors such as the system clock speed, the bus length, the amount of current that the output drivers can drive, the supply voltages, the spacing and width of the wires or traces making up the bus, and the physical layout of the bus itself. Clock, or control, signals serve the purpose of marking the passage of time, thereby controlling the transfer of information from one storage location to another. The memory controller 22 is connected to a central processing unit (CPU) 40 and other system components 50, such as a graphics control unit, over bus 45.
As signals pass over a bus and through device interfaces, the signals experience propagation delays. Propagation delays are affected by variables such as temperature, supply voltage and process parameters (which determine physical characteristics of the devices sending and receiving the signals). For example, at a low operating temperature with a high supply voltage, signals may be transmitted with a relatively short delay. Alternatively, at a low supply voltage and high operating temperature, a significantly longer delay may be experienced by transmitted signals.
Variations in the process parameters, which result in variations in the performance of otherwise identical devices, cause devices either on a single bus, or devices on parallel buses to experience different signal propagation delays. The load on each bus, which depends on the number of devices connected to the bus, may also affect signal propagation. In sum, the phase relationships between transmitted and received signals, are affected by numerous factors, some of which may change during the operation of a system. Small changes in propagation delays can result in data transfer errors, especially in systems with very high bit (or more generally, symbol) transfer rates, and thus very short bit (or symbol) times. In order to account for actual propagation delays, it is desirable, especially in systems with very high bit (or symbol) transfer rates (e.g., without limitation, 250 Mb/s or higher) to synchronize signal transmitters and receivers, to account for actual propagation delays. The present invention provides systems and methods for dynamically synchronizing signal transmitters and receivers, even when the variations in propagation delays caused by temperature, voltage, process and loading variations exceed an average symbol time interval. Normally, a variation in propagation delay of even a half symbol time interval will cause a memory system or data transfer system to fail, because movement of a half symbol time will cause the data sample point to move from the center of the data eye to the edge of the data eye. Change in the propagation delay of more than a half symbol time will, in conventional prior art systems, cause the wrong symbol to be sampled by the receiving device. In the present invention, such changes in propagation delay are automatically “calibrated out” by the use of dynamic propagation delay calibration apparatus and methods.